Hardware Design
Hardware Design Solutions
AISOC Systems offers flexible models depending on customer needs from Spec to System.
Our Service offerings include:
- SOC Design
- Verification
- Physical Design
SOC Design
With derivative SoC designs, the company’s core product team focuses on future roadmap development thereby emerging as an engineering partner to extend its intellectual contribution in the existing SoC development, investment to meet market needs and derivative market opportunities. With spec handoff designs, our company leverages its deep experience in Networking, Telecom, Storage, and Computing to take the lead in defining the SoC architecture and system design.
- Process technology nodes: eg (14nm, 20nm, 28nm, 40nm, 65nm, 90nm, 130nm)
- Low power – architecture and physical implementation
- High-performance – pipeline design and I/Os
- Multiple clock domains
- High-speed Interfaces: [SERDES (10G serial, XAUI, PCIe), PCI-Express, USB 2.0/3.0, Thunderbolt SAS, ATA/SATA and Fiber Channel ]
- High-performance Memory Sub-Systems – DDR2/DDR3 Memory controllers, Flash controller
- Networking, Routing, Switching, Ethernet, 802.x, Cellular/Baseband, Tablets, Data Storage, Graphics, Video
- All major CPU, GPU, and DSP architectures including multi-core ARM/custom architectures
Verification
Verification Deliverables
- ASIC Chip-Verification
- SOC-Verification
- IP-Block Verification
- Sub-Block Module Level Verification
- Verification-IP Development
- Verification Test plan, Strategy
- Functionality Matrix Coverage
- Coverage Analysis and Closure
Verification Methodologies:
- Adapting the Industrial Standards using SV-UVM, SV-OVM
- Upgrading of legacy Testbenches to UVM
- Constraint Random Driven Verification
- Integration of Assertion Based Verification using SVA
- Formal Verification
- Performance Testing
- Automation using scripts in Tcl, Shell, Perl, Python.
- Proficiency in legacy verification environments
Physical Design
We provide a complete suite of physical implementation services focused on, low-power high performance designs at various process nodes. We have expertise in synthesis, DFT and Physical design and implementation including STA signoff.
Our goal is to successfully tape-out on time and with best quality.
Our team has proven experience in designing highly complex ASICs which include network processors, graphic processors, low-power designs with design sizes ranging from 1 million gates to over 50 million gates across all major foundries and at various technologies nodes ranging from 130nm to 28nm.
With a defined 4-phase milestone approach with our customers, we’re able to identify issues, create solutions and provide feedback to customer teams during the entire physical implementation process and ensure an aggressive schedule to tapeout without sacrificing quality